Verification

ASIC verification takes as much as up to 70 percent of the ASIC development time and resources. Verification problems are growing exponentially with every new design. SPLITZDESIGN provides quality and time efficient verification services to customers. To augment your development team SPLITZDESIGN’s Verification Expertise Center offers an extensive set of services in system verification and modeling. Our Verification Expertise center provides experienced, independent and dedicated resources to verify your design with a high degree of confidence. This helps ensure that your design will work correctly the first time. Specifically, our engineers have experience in and can help you with:

• Specification and Requirements Review
• Creation of Functional Test Plans
• Design and Creation of Verification environment
• Utilization of Latest Reuse Methodologies
• Creation of fully Automated and Self-checking Test Suites
• Test runs, Collection and Interpretation of coverage data
• Assistance in debug efforts and provide meaningful design feedback

SPLITZDESIGN can adapt to customer’s verification methodology and environment.

Our comprehensive service spectrum available individually or as full turnkey solutions across various silicon phases is listed below:

Module to Chip Level verification

• Define verification strategy to ensure first time right silicon
• Define the verification environment for all levels of verification for maximum coverage
• Develop comprehensive test plans for module level and chip level to achieve zero bugs.
• Develop module and chip level coverage plan for maximum functions coverage with random testing
• Develop highly efficient module and chip level verification environment with maximum reusability
• Integration of industry standard VIP for maximum productivity gain.
• Development of module and chip level assertions.
• Develop efficient regression environment to reduce simulation time.
• Extensive experience in verification various interfaces
• Excellent experience in verification using SystemVerilog, Vera, e, SystemC/C++, Verilog, VHDL and mixed languages.

Coverage driven verification

• Develop verification strategy based on industry standard methodologies like VMM, RVM, AVM, eRM, UVM.
• Develop coverage plan for maximum functions coverage with random testing
• Develop environment for coverage driven verification using SystemVerilog, Vera or e.
• Coverage development on legacy verification environment.
• Coverage plans for standard interfaces.

Assertion based verification

• White box assertion development for design IPs.
• Experience in development of Assertion IPs for standard interfaces
• Develop assertions using SVA, PSL and OVA.

Tools

SPLITZDESIGN has expertise in variety of tools used in Verification. As strategic partners with several tool manufacturers, we can determine which tool will work best for your particular application and get it up and running efficiently and quickly. Verification tools used in the past include:

• Verisity Specman
• Synopsys Vera
• Assembly Languages for CPU & BFMs
• Perl, TCL/TK scripting
• Bugzilla and other error reporting/tracking systems
• PLI and FLI interfaces for custom verification environments

Experience

SPLITZDESIGNhas rich experience to extensively verify complex designs. Our engineers have successfully verified designs ranging from 5K to over 5 Million gates. Recent experience includes:

• Creation and maintenance of reusable verification components
• System on a chip verification experience
• Vera verification with reusable modules